Clock distribution network designers face the problem of designing clock distribution networks that distribute clock signals throughout an integrated circuit device or system with a minimal level of clock skew. Clock skew is the difference in arrival times of clock edges to different parts of a system. Synchronous digital logic requires a precision synchronization of clock signals for the latching of data. Ideal synchronous logic relies on the simultaneous arrival of clock signals to all circuits located in the system. Clock skew affects distribution network design by reducing the maximum operating frequency that is attainable by a system. This is because the system has to be designed taking worst case skew into account for it to operate reliably.
The principle cause of clock skew in clock distribution networks is the variation in the routing impedance of various branches of the clock distribution network. Consequently, clock skew may arise within an individual integrated circuit die even where an equal length clock distribution network such as an H-Tree is employed. As a result, a skew budget derived from a worst case skew analysis must be adhered to by network designers in order for the circuits supplied by the network to operate reliably. A good rule of thumb is that the clock skew budget may not exceed approximately 10% of the cycle time. Hence for a 1 GHz clock frequency, which corresponds to a 1 ns cycle time, the tolerable clock skew may be less than or equal to 100 ps. If skew increases beyond a certain time period, setup and hold time problems may be unavoidable. It should be appreciated, however, that as VLSI clock frequencies increase beyond 1 GHz, the distribution network design constraints presented by clock skew become even more challenging.
Auto routing tools may be used to build balanced buffer trees for clocks based on operator provided constraints. However, as circuit components (flip flops etc.) increase it becomes more difficult at the block level for the auto routing tool to provide a buffer tree that balances clock skew. Building chip level buffer trees using auto routing tools become more difficult as the number of blocks in a design increase. The process is further complicated by the need to have provided a timing number for each of the blocks in a design. As the design size increases to levels that encompass millions of gates, the clock skew exhibited by a network may increase prohibitively. Within a single block clock skew may be manageable, but may become increasingly difficult as the designer progresses to the chip level. Moreover, as systems become more complicated utilizing increasingly faster operating frequencies, it becomes extremely difficult to resolve clock skew problems at the chip level (e.g., using the balanced buffer tree approach) without substantial manual input.
Generally, there are two basic distribution schemes that are currently in common use. The first employs balanced buffer tree networks at both the block and chip levels of an integrated circuit design such as is shown in FIG. 1. FIG. 1 shows clock pin 101, individual integrated circuit blocks 103, integrated circuit 105, block level buffer tree network 107, and chip level buffer tree network 109. According to this approach, the clock inputs to the individual blocks 103 of the integrated circuit are treated as leaf pins of the chip level buffer tree network 109. A drawback of this approach includes the difficulty in achieving a balanced skew across the blocks of the integrated circuit 105 at the chip level. This is a consequence of the difficulty posed in predicting the routing characteristics of the routes traversed by clock signals (input at clock pin 101) that are transmitted through the clock distribution network. In addition, according to this methodology, the top level clock plan cannot be designed until each block level buffer tree network 107 inside the integrated circuit blocks 103 are placed and routed.
The second conventional clock distribution scheme employs a flat clock mesh network for distributing clock signals to all the circuit components in a chip. Using this method, grid meshes are used to connect each component within a block. Skew for each component may then be ascertained (predicted) and utilized in arranging a network of buffers at the periphery of the block to adjust the delays for each component (care should be taken that the introduction of delay buffers do not introduce too much delay). However, because the delay of each component in the system must be managed, systems that employ millions of components require extensive manual layout work. Additional drawbacks of this scheme include its lack of hierarchical intricacy, its routing track intensiveness, the long turn around times manifest in its production, and the lack of tool support available for creation and analysis purposes. It should be appreciated that, skew prediction at the chip level is very difficult with either of these schemes, and accommodating multiple clock domains may present significant challenges.